GS82582T19 Datasheet, PDF (8/27 Pages) GSI Technology – 288Mb SigmaDDR-II+TM Burst of 2 SRAM

GS82582T19/37GE-450/400/375/333
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20 s prior to issuing read and write commands. See the t_KInit
timing parameter in the AC Electrical Characteristics section.
Note:
The t_KInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, t_KInit is greater than t_KLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2 s). Consequently, the 20 s associated with t_KInit is sufficient to cover the t_KLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20 s period.
Also, t_KInit only needs to be met once, immediately after power-up, whereas t_KLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).
Rev: 1.04 4/2016
8/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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