GS81313LD36GK-625 Datasheet, PDF (8/26 Pages) GSI Technology – 4Mb x 36 and 8Mb x 18 organizations available

GS81313LD18/36GK-833/714/625
Clock Truth Table
Previous
Operation
SA
R
W
Current Operation
D
Q
(t_n–1)
CK CK CK
(t_n) (t_n) (t_n)
(t_n)
KD KD KD KD CQ CQ CQ CQ
(t_n-1) (t_n-½)
(t_n)
(t_n+½) (t_n+3) (t_n+3½) (t_n+4) (t_n+4½)
NOP
X11
NOP
X
X
—
—
0
—
Write
X1X
NOP
D3
D4
—
—
0
—
Read
XX1
NOP
X
X
—
—
Q3
Q4
—
NOP
V10
Write
D1
D2
D3
D4
0
—
Read
VX0
Write
D1
D2
D3
D4
Q3
Q4
—
NOP
V0X
Read
X
X
—
—
Q1
Q2
Q3
Q4
Write
V0X
Read
D3
D4
—
—
Q1
Q2
Q3
Q4
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations.
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations.
4. Q pins are driven Low for one cycle in response to NOP and Write commands, 3 cycles after the command is sampled, except when pre-
ceded by a Read command.
Rev: 1.13 7/2016
8/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology