GS8330LW36C Datasheet, PDF (7/30 Pages) GSI Technology – 36Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM

CK
Address
ADV
/E1
ADV
/BA
/BB
DQA0-DQA8
DQB0-DQB8
CQ
Preliminary
GS8330LW36/72C-250/200
Two Byte Write Control Example with Late Write SigmaRAM
W rite
W rite
W rite
No n - W rite
W rite
A
B
C
D
E
F
DA
DB
DE
DA
DC
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.
The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter
generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM
by driving the ADV pin low, into Load mode.
Rev: 1.00 6/2003
7/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.