GS82564Z36GD-250I Datasheet, PDF (7/35 Pages) GSI Technology – 288Mb Pipelined and Flow Through Synchronous NBT SRAM

165-Bump BGA Pin Description
Symbol
A0, A1
An
A18
DQA
DQB
DQC
DQD
BA, BB, BC, BD
CK
CKE
W
E1
E3
E2
FT
G
ADV
Type
I
I
I
I/O
I
I
I
I
I
I
I
I
I
I
ZQ
I
ZZ
I
LBO
I
TMS
I
TDI
I
TDO
O
TCK
I
MCH
—
V_DD
I
V_SS
I
V_DDQ
I
NC
—
GS82564Z18/36(GB/GD)
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Address Input
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Flow Through / Pipeline Mode Control
Output Enable; active low
Burst address counter advance enable; active high
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Rev: 1.02 5/2017
7/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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