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GS8180QV18BD-200 Datasheet, PDF (7/28 Pages) GSI Technology – 18Mb Burst of 2 SigmaQuad SRAM | |||
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GS8180QV18/36BD-200/167
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
Beat 1
0
1
Beat 2
1
0
D0âD8
Data In
Donât Care
D9âD17
Donât Care
Data In
Resulting Write Operation
Beat 1
D0âD8
Written
Beat 1
D9âD17
Unchanged
Beat 2
D0âD8
Unchanged
Beat 2
D9âD17
Written
Output Register Control
SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.02b 11/2011
7/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology
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