GS8170DW36AC Datasheet, PDF (6/32 Pages) GSI Technology – 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM

GS8170DW36/72AC-350/333/300/250
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement
Pipeline mode NBT SRAMs.
SigmaRAM Double Late Write with Pipelined Read
Read
W rite
Read
W rite
Read
CK
Address
A
B
C
D
E
F
ADV
/E1
/W
DQ
QA
DB
QC
DD
CQ
Key
Hi-Z
Access
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
Read
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
W
Ba
Bb
Bc
Bd
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Rev: 1.04 4/2005
6/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology