GS8128036GT-250I Datasheet, PDF (5/24 Pages) GSI Technology – 8M x 18, 4M x 32, 4M x 36 144Mb Sync Burst SRAMs

GS8128018/32/36GT-400/333/250/200
TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB
BC, BD
CK
GW
E1, E3
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V_DD
V_SS
V_DDQ
NC
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
NU
—
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect
Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may be
left unconnected, tied Low (to V_SS), or tied High (to V_DDQ or V_DD).
Rev: 1.01 5/2017
5/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology