GS88118AT Datasheet, PDF (4/36 Pages) GSI Technology – 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs

TQFP Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1
E2
G
ADV
ADSP, ADSC
ZZ
TMS
TDI
TDO
TCK
FT
LBO
V_DD
V_SS
V_DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.04 3/2005
4/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology