GS8673ED36BK-675 Datasheet, PDF (4/31 Pages) GSI Technology – 72Mb SigmaQuad-IIIe Burst of 4 ECCRAM

GS8673ED18/36BK-675/625/550/500
Pin Description
Symbol
Description
SA
D[35:0]
Q[35:0]
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
Address—Read or Write Address is registered on ↑CK.
Write Data—Registered on ↑KD and ↑KD during Write operations.
D[17:0]—x18 and x36.
D[35:18]—x36 only.
Read Data—Driven by ↑CK and ↑CK, and synchronized with ↑CQ and ↑CQ during Read operations.
Q[17:0]—x18 and x36.
Q[35:18]—x36 only.
Read Data Valid—Driven high one half cycle before valid Read Data.
Primary Input Clocks—Dual single-ended. For Address and Control input latching, internal timing control,
and Read Data and Echo Clock output timing control.
Write Data Input Clocks—Dual single-ended. For Write Data input latching.
KD0, KD0—latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1—latch Write Data (D[35:18] in x36, D[17:9] in x18).
Echo Clocks—Free running source synchronous output clocks.
R
W
ADZT1
DLL
RST
RLM[1:0]
ZQ
ZT
Read Enable—Registered on ↑CK. R = 0 initiates a Read operation.
Write Enable—Registered on ↑CK. W = 0 initiates a Write operation.
Address and Write Data Input Termination Pull-Up Enable—Registered on↑CK.
ADZT1 = 0: enables termination pull-up on Address (SA), Write Data (D) inputs.
ADZT1 = 1: disables termination pull-up on Address (SA), Write Data (D) inputs.
DLL Enable—Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Reset—Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Read Latency Select 1:0—Must be tied High or Low.
RLM[1:0] = 00: reserved.
RLM[1:0] = 01: selects 2.0 cycle Read Latency.
RLM[1:0] = 10: selects 3.0 cycle Read Latency.
RLM[1:0] = 11: reserved.
Output Driver Impedance Control Resistor Input—Must be connected to V_SS through an external
resistor RQ to program output driver impedance.
Input Termination Impedance Control Resistor Input—Must be connected to V_SS through an external
resistor RT to program input termination impedance.
Type
Input
Input
Output
Output
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Rev: 1.06 5/2012
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology