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GS8342T08E Datasheet, PDF (4/37 Pages) GSI Technology – 36Mb SigmaCIO DDR-II Burst of 2 SRAM
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Preliminary
GS8342T08/09/18/36E-333/300/267*/250/200/167
4M x 9 SigmaCIO DDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
CQ
MCL/SA
(72Mb)
SA
R/W
NC
K
NC
LD
SA
SA
CQ
B
NC
NC
NC
SA
NC
K
BW
SA
NC
NC
DQ4
C
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ5
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ2
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ8
SA
SA
C
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 is set to 0 at the
beginning of each access.
2. MCL = Must Connect Low
Rev: 1.02 8/2005
4/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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