GS8180D18D Datasheet, PDF (4/28 Pages) GSI Technology – 18Mb Burst of 4 SigmaQuad SRAM

GS8180D18D-250/200/167/133/100
interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The
user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at
hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
Burst of 4 SigmaQuad SRAM DDR Read
The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. The
four resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the
C, the rising edge of C after that, the next rising edge of C, and finally by the next rising edge of C.
Burst of 4 Double Data Rate SigmaQuad SRAM Read First
Read A
NOP
Read B
Write C
Read D
Write E
NOP
K
K
Address
A
R
W
BWx
D
C
C
Q
B
C
D
E
C
C+1
C+2
C+3
E
E+1
A
A+1
A+2
A+3
B
B+1
B+2
B+3
D
D+1
D+2
Rev: 2.04 4/2005
4/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology