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GS81314PQ18 Datasheet, PDF (39/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Multi-Bank ECCRAM™ | |||
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Revision History
Rev. Code
GS81314PQ1836GK_r1
GS81314PQ1836GK_r1.01
GS81314PQ1836GK_r1.02
GS81314PQ1836GK_r1.03
GS81314PQ1836GK_r1.04
GS81314PQ1836GK_r1.05
GS81314PQ1836GK_r1.06
GS81314PQ1836GK_r1.07
GS81314PQ1836GK_r1.08
GS81314PQ1836GK_r1.09
GS81314PQ18/36GK-133/120/106
Types of Changes
Format or Content
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Revisions
⢠Creation of new datasheet
⢠Changed Loopback Latency to 7 cycles, regardless of Read Latency.
⢠Removed leaded BGA package support.
⢠Removed 4th digit from all speed bins.
⢠Redefined Bank Address pins.
⢠Increased VDD (max) to 1.35V.
⢠Added package thermal impedances.
⢠Redefined OFR[2:0] bits in Configuration Reg #1 as RSVD[2:0].
⢠Revised tKHKDH specs.
⢠Revised tKHQV, tKHQX, and tKHCQH specs.
⢠Revised tCQHQV and tCQHQX specs.
⢠Revised tIPW specs.
⢠Banner changed to âPreliminaryâ, to reflect ES status.
⢠Add IDD specifications.
⢠Changed -125 speed bin to -120. Changed -110 speed bin to -106.
Removed -100 speed bin.
⢠Removed RL=5 support (created new RL=5 -specific datasheet with
no bank restrictions; see GS81314PQ1937GK).
⢠Removed R(n) <> R(n-1) bank restrictions from all but -133 devices.
⢠Reduced VDD (min) requirement for -120 speed bin to 1.15V, to allow
for 1.2V nominal VDD.
⢠Removed âPreliminaryâ from data sheets.
⢠Increased VDD (min) to 1.2V for 1066 MHz and 1200 MHz speed
bins. VDD (min) is now the same value for all speed bins.
Rev: 1.09 5/2016
39/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
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