GS816218BB Datasheet, PDF (30/37 Pages) GSI Technology – 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs

GS816218/36B(B/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
3.3 V Test Port Input High Voltage
V_IHJ3
2.0
V_DD3 +0.3
3.3 V Test Port Input Low Voltage
V_ILJ3
–0.3
0.8
2.5Test Port Input High Voltage
V_IHJ
0.6 * V_DD
V_DD2 +0.3
2.5 Test Port Input Low Voltage
V_ILJ
–0.3
0.3 * V_DD
TMS, TCK and TDI Input Leakage Current
I_INHJ
–300
1
TMS, TCK and TDI Input Leakage Current
I_INLJ
–1
100
TDO Output Leakage Current
I_OLJ
–1
1
Test Port Output High Voltage
V_OHJ
1.7
—
Test Port Output Low Voltage
V_OLJ
—
0.4
Test Port Output CMOS High
V_OHJC V_DDQ – 100 mV
—
Test Port Output CMOS Low
V_OLJC
—
100 mV
Notes:
1. Input Under/overshoot voltage must be – V > Vi < V_DDn + V maximum, with a pulse width not to exceed 50% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DDQ supply.
6. I_OHJ = –4 mA
7. I_OLJ = + 4 mA
8. I_OHJC = –100 uA
9. I_OHJC = +100 uA
JTAG Port Timing Diagram
Unit Notes
V
1
V
1
V
1
V
1
uA
2
uA
3
uA
4
V 5, 6
V 5, 7
V 5, 8
V 5, 9
TCK
TDI
TMS
TDO
Parallel SRAM input
tTKC
tTKH
tTH
tTS
tTH
tTS
tTKQ
tTH
tTS
tTKL
Rev: 1.04 9/2005
30/37
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology