GS81302Q07E-318I Datasheet, PDF (28/28 Pages) GSI Technology – JEDEC-standard pinout and package

GS81302Q07/10/19/37E-318/300/250/200
SigmaQuad-II+ SRAM Revision History
File Name
Format/Content
81302Q1937_r1
81302Q1937_r1_01
81302Q1937_r1_02
Description of changes
Creation of datasheet
(Rev1.00a: removed CQ reference from SAMPLE-Z section in
JTAG Tap Instruction Set Summary)
Added 333 MHz speed bin
Added Op Currents
Updated to MP status
(Rev1.02a: Editorial updates)
(Rev1.02b: Changed 333 MHz to 318 MHz)
(Rev1.02c: Updated cycle time for 318 MHz)
(Rev1.02d: Corrected AC Char for top bin)
(Rev1.02e: Corrected erroneous speed bin references in ordering
information table)
(Rev1.02f: Corrected erroneous information in Input and Output
Leakage Characteristics table)
Rev: 1.02f 8/2017
28/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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