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GS81314LD18GK-106 Datasheet, PDF (24/40 Pages) GSI Technology – Burst of 4 Multi-Bank ECCRAM | |||
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GS81314LD18/36GK-133/120/106
Input Signal
Register Bits
Pull-Down Impedance (RINL)
CZT[1:0] = 00
off
R, W, MRW
CZT[1:0] = 01
CZT[1:0] = 10
RT ï± 15%
RT*2 ï± 20%
CZT[1:0] = 11
reserved
DZT[1:0] = 00
off
DZT[1:0] = 01
RT ï± 15%
D
DZT[1:0] = 10
RT*2 ï± 20%
DZT[1:0] = 11
reserved
Notes:
1. RINL and RINH apply when 105ïï ï£ RT ï£ 135ïï®
2. The mismatch between RINL and RINH is less than 10%, guaranteed by design.
3. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Pull-Up Impedance (RINH)
off
RT ï± 15%
RT*2 ï± 20%
reserved
off
RT ï± 15%
RT*2 ï± 20%
reserved
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the deviceâs operating currents being higher.
Rev: 1.09 5/2016
24/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
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