GS8673EQ18BK-625I Datasheet, PDF (22/31 Pages) GSI Technology – On-Chip ECC with virtually zero SER

GS8673EQ18/36BK-675/625/550/500
SigmaQuad-IIIe Burst of 2, RL = 3
Rd + Wr Rd Only Wr Only Rd + Wr Wr Only Rd Only NOP Rd + Wr Rd + Wr NOP Rd Only
KD
KD
D D21 D22
t_KHKH t_KHKL t_KLKH t_KHKH
t_DVKH
t_KHDX
D41 D42 D61 D62 D71 D72
t_DVKH
t_KHDX
DA1 DA2 DC1 DC2
t_KHKDH
CK
CK
t_KHKDH
SA A1 A2 A3
R
W
Q
t_KHKH t_KHKL t_KLKH t_KHKH
t_AVKH
t_KHAX
A4 A5 A6
A7 A8
t_IVKH t_KHIX
t_AVKH
t_KHAX
A9 AA AB AC
AD
t_KHQV
t_KHQX
Q11 Q12 Q31 Q32
Q51 Q52
Q81 Q82
QVLD
t_KHCQH
t_CQHQV
t_CQHQX
t_CQHQV
t_CQHQX
t_CQHQX
t_CQHQV
CQ
t_CQHCQH
CQ
Note: The Q state during non-Reads depicted in this diagram (Q=Low) applies when D input termination is enabled (MZT=01 or 10).
When D input termination is disabled (MZT=00), the Q state during non-Reads is High-Z.
Rev: 1.06 5/2012
22/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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