GS81314PQ19 Datasheet, PDF (22/39 Pages) GSI Technology – Burst of 2 Single-Bank ECCRAM

GS81314PQ19/37GK-933/800
Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
During Memory Mode, CK and CK latch address (SA) inputs, and CK latches control (R, W, MRW) inputs.
During Register Write Mode, CK latches address and control inputs.
During Loopback Mode, CK and CK latch address, control, and write data clock (KD, KD) inputs.
During Memory Mode, KD[1:0] and KD[1:0] latch particular write data (D, DINV) inputs, as follows:
• KD0 and KD0 latch D[17:0], DINV[1:0] in x36 devices, and D[8:0], DINV0 in x18 devices.
• KD1 and KD1 latch D[35:18], DINV[3:2] in x36 devices, and D[17:9], DINV1 in x18 devices.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0 and 180 phase clocks from CK
that control read data output clock (CQ, CQ), read data (Q, QINV), and read data valid (QVLD) output timing, as follows:
• CK+0 generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• CK+180 generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more
information.
CQ[1:0] and CQ[1:0] align with particular Q, QINV, and QVLD outputs, as follows:
• CQ0 and CQ0 align with Q[17:0], QINV[1:0], QVLD0 in x36 devices, and Q[8:0], QINV0, QVLD0 in x18 devices.
• CQ1 and CQ1 align with Q[35:18], QINV[3:2], QVLD1 in x36 devices, and Q[17:9], QINV1, QVLD1 in x18 devices.
Rev: 1.02 3/2016
22/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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