GS8673EQ18BK-625 Datasheet, PDF (20/31 Pages) GSI Technology – On-Chip ECC with virtually zero SER

GS8673EQ18/36BK-675/625/550/500
AC Electrical Characteristics (independent of device speed grade)
Parameter
Symbol
Min
Max
Units Notes
Input Clock Timing
Clk High Pulse Width
t_KHKL
0.45
—
cycles 1
Clk Low Pulse Width
t_KLKH
0.45
—
cycles 1
Clk High to Clk High
t_KHKH
0.45
0.55
cycles 2
Clk High to Write Data Clk High
t_KHKDH
-200
200
ps
3
DLL Lock Time
t_Klock
65,536
—
cycles 4
Clk Static to DLL Reset
t_Kreset
30
—
ns 5,11
Output Timing
Clk High to Data Output Valid
t_KHQV
—
400
ps
6
Clk High to Data Output Hold
t_KHQX
-400
—
ps
6
Clk High to Data Output High-Z
t_KHQHZ
—
400
ps
7
Clk High to Data Output Low-Z
t_KHQLZ
-400
—
ps
7
Clk High to Echo Clock High
t_KHCQH
-400
400
ps
8
Echo Clk High to Echo Clock High
t_CQHCQH
t_KHKH (min) - 50
t_KHKH (max) + 50
ps 9,11
Echo Clk High to Echo Clock High
t_CQHCQH
t_KHKH (min) - 50
t_KHKH (max) + 50
ps 10,11
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal unless otherwise noted.
1. Parameters apply to CK, CK, KD, KD.
2. Parameter specifies ↑CK → ↑CK and ↑KD → ↑KD requirements.
3. Parameter specifies ↑CK → ↑KD and ↑CK → ↑KD requirements.
4. V_DD slew rate must be < 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
5. Parameter applies to CK.
6. Parameters apply to Q, and are referenced to ↑CK.
7. Parameters apply to Q when MZT[1:0] = 00, and are referenced to ↑CK. They are measured at ± 50 mV from steady state voltage.
8. Parameter specifies ↑CK → ↑CQ timing.
9. Parameter specifies ↑CQ → ↑CQ timing. t_KHKH (min) and t_KHKH (max) are the minimum and maximum input delays from ↑CK to ↑CK
applied to the device, as determined by the Absolute Jitter associated with those clock edges.
10. Parameter specifies ↑CQ → ↑CQ timing. t_KHKH (min) and t_KHKH (max) are the minimum and maximum input delays from ↑CK to ↑CK
applied to the device, as determined by the Absolute Jitter associated with those clock edges.
11. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.06 5/2012
20/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology