|
GS8182D09BGD-333 Datasheet, PDF (20/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM Burst of 4 SRAM | |||
|
◁ |
GS8182D08/09/18/36BD-400/375/333/300/250/200/167
AC Electrical Characteristics
Parameter
-400
-375
-333
-300
-250
-200
-167
Symbol
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
2.5 8.4 2.67 8.4 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
tTKC Variable
tKCVar
â 0.2 â 0.2 â 0.2 â 0.2 â 0.2 â 0.2 â 0.2 ns 6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.0
â 1.13 â 1.2
â 1.32 â
1.6 â 2.0
â
2.4
â ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.0
â 1.13 â 1.2
â 1.32 â
1.6 â 2.0
â
2.4
â ns
K to K High
C to C High
tKHKH
tCHCH
1.0
â 1.13 â 1.35 â 1.49 â
1.8
â
2.2
â
2.7
â ns
K to K High
C to C High
tKHKH
tCHCH
1.0
â 1.13 â 1.35 â 1.49 â
1.8
â
2.2
â
2.7
â ns
K, K Clock High to C, C Clock High tKHCH
0 1.1 0 1.2 0 1.3 0 1.45 0 1.8 0
2.3 0 2.8 ns
DLL Lock Time
tKCLock 1024 â 1024 â 1024 â 1024 â 1024 â 1024 â 1024 â
6
K Static to DLL reset
Output Times
tKCReset
30
â
30
â
30
â
30
â
30
â
30
â
30
â ns
K, K Clock High to Data Output Valid tKHQV
C, C Clock High to Data Output Valid tCHQV
â 0.45 â 0.45 â 0.45 â 0.45 â 0.45 â 0.45 â 0.5 ns 4
K, K Clock High to Data Output Hold tKHQX
C, C Clock High to Data Output Hold tCHQX
â0.45 â â0.45 â â0.45 â
â0.45
â â0.45 â â0.45 â
â0.5
â ns 4
K, K Clock High to Echo Clock Valid tKHCQV
C, C Clock High to Echo Clock Valid tCHCQV
â 0.45 â 0.45 â 0.45 â
0.45 â 0.45 â 0.45 â
0.5 ns
K, K Clock High to Echo Clock Hold tKHCQX
C, C Clock High to Echo Clock Hold tCHCQX
â0.45
â
â0.45
â
â0.45
â
â0.45
â â0.45 â â0.45 â
â0.5
â ns
CQ, CQ High Output Valid
tCQHQV â 0.25 â 0.25 â 0.25 â 0.27 â 0.30 â 0.35 â 0.40 ns 8
CQ, CQ High Output Hold
tCQHQX â0.25 â â0.25 â â0.25 â â0.27 â â0.30 â â0.35 â â0.40 â ns 8
CQ Phase Distortion
tCQHCQH
tCQHCQH
0.9
â
1.0
â 1.10 â 1.24
â 1.55 â 1.95 â 2.45 â ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
â 0.45 â 0.45 â 0.45 â 0.45 â 0.45 â 0.45 â 0.5 ns 4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
â0.45
â
â0.45
â
â0.45
â
â0.45
â â0.45 â â0.45 â
â0.5
â ns 4
Setup Times
Address Input Setup Time
tAVKH
0.4 â 0.4 â 0.4 â
0.4
â
0.5 â 0.6 â 0.7 â ns 1
Control Input Setup Time (RW, LD) tIVKH
0.4 â 0.4 â 0.4 â 0.4 â 0.5 â 0.6 â 0.7 â ns 2
Control Input Setup Time (BWX,
NWX)
tIVKH
0.28 â 0.28 â 0.28 â
0.3
â 0.35 â
0.4
â
0.5
â ns 3
Data Input Setup Time
tDVKH
0.28 â 0.28 â 0.28 â
0.3
â 0.35 â
0.4
â
0.5
â ns
Rev: 1.03d 11/2011
20/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology
|
▷ |