GS81314PD37GK-933I Datasheet, PDF (20/39 Pages) GSI Technology – Burst of 4 Single-Bank ECCRAM

GS81314PD19/37GK-933/800
Data Bus Inversion
Because the POD I/O standard employs high-side (pull-up) termination only, signals driven High consume less power than those
driven Low. Consequently, these devices provide the ability to invert all data pins on a per byte basis, such that any transmitted data
byte always contains more 1s than 0s, thereby reducing average I/O power as well as SSO noise. To accomplish this, one data in-
version (DINV, QINV) bit is utilized per 9-bit data (D, Q) byte.
During Write operations, the controller inverts a particular 9-bit write data byte before transmitting it to the SRAM if it contains less
than 5 High bits; otherwise, it transmits the data byte uninverted. If it inverts the data byte, the controller drives the corresponding
write data inversion bit High; otherwise, it drives it Low. Upon receiving the write data byte, the SRAM uses the state of the corre-
sponding write data inversion bit to determine whether or not to invert the data byte before storing it in the memory array.
During Read operations, the SRAM inverts a particular 9-bit read data byte before transmitting it to the controller if it contains less
than 5 High bits; otherwise, it transmits the data byte uninverted. If it inverts the data byte, the SRAM drives the corresponding read
data inversion bit High; otherwise, it drives it Low. Upon receiving the read data byte, the controller uses the state of the correspond-
ing read data inversion bit to determine whether or not to invert the data byte before utilizing it.
With this implementation, each 10-bit data group (nine data bits plus one data inversion bit) is guaranteed to have no more than five
pins driven low at any given time. Consequently, no more than five pins in each group can switch in the same direction during each
bit time, reducing SSO noise effects.
Note: Data Inversion can be enabled and disabled via register bit DI.
Read Latency
Read Latency (i.e. the number of cycles from read command input to first read data output) is specified as follows:
Read Latency
5 cycles
Comment
First read data output 5 cycles after read command input
Note: The RLM register bit must be written to “0” in these devices prior to initiating Read operations, to set Read Latency = 5 cycles.
Write Latency
Write Latency (i.e. the number of cycles from write command input to first write data input) is specified as follows:
Write Latency
-1 cycle
Comment
First write date input 1 cycle before write command input
Read / Write Coherency
These devices are fully coherent. That is, Read operations always return the most recently written data to a particular address, even
when a Read operation to a particular address occurs one cycle after a Write operation to the same address.
Rev: 1.02 3/2016
20/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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