GS81314PD19 Datasheet, PDF (19/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 4 Single-Bank ECCRAM™

GS81314PD19/37GK-933/800
Address Bus Utilization
The address bus is a non-multiplexed SDR bus. One memory address may be loaded per cycle - a read address at CK or a write
address at CK; consequently only one memory operation - a Read or a Write - may be initiated per clock cycle. The address bus is
also sampled at CK during a Register Write operation.
Address Bit Encoding
Command
Addr
Load
Device
21
20
19
18
17
16
15
14
SA Address Bits
13 12 11 10 9 8
7
6
5
4
3
2
1
0
x36 NU
Address
NU
Read
CK
x18
Address
NU
x36 NU
Address
NU
Write
CK
x18
Address
NU
Register
Write
CK
x36 NU X X X X X X X X X X
x18 X X X X X X X X X X X
Register Data
Register Data
Register # NU
Register # NU
Rev: 1.02 3/2016
19/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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