GS81314LD18GK-133I Datasheet, PDF (19/40 Pages) GSI Technology – Burst of 4 Multi-Bank ECCRAM

GS81314LD18/36GK-133/120/106
Address Bus Utilization and Bank Access Restrictions
The address bus is a non-multiplexed SDR bus. One memory address may be loaded per cycle - a read address at CK or a write
address at CK; consequently only one memory operation - a Read or a Write - may be initiated per clock cycle. The address bus is
also sampled at CK during a Register Write operation.
Address Bit Encoding
Command
Addr
Load
Device
21
20
19
18
17
16
15
14
SA Address Bits
13 12 11 10 9 8
7
6
x36 NU
Address
BA
Read
CK
x18
Address
BA
x36 NU
Address
BA
Write
CK
x18
Address
BA
Register
Write
CK
x36 NU X X X X X X X X X X
x18 X X X X X X X X X X X
Register Data
Register Data
Note: BA = Bank Address
543210
Address BA NU
Address BA NU
Address BA NU
Address BA NU
Register # NU
Register # NU
Bank Access Restrictions
1. In all devices, Read in cycle “n” must be to a different bank than Write in cycle “n-4” (due to Write Buffering).
Note: Bank restriction #1 (the only restriction in SIO-B4 devices) can be avoided by always initiating Reads “in phase” - that is, by
always initiating Reads an even number of cycles apart.
Consider a typical sequence of alternating Read and Write operations:
R -> W -> R -> W -> R -> W -> R -> W -> R -> W -> R -> W.
In this case the Reads are always “in phase” because they always occur 2 cycles apart. Consequently, when a Read occurs in cycle
“n”, the operation in cycle “n-4” is always a Read, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where NOPs replace Read and Write operations in the typical sequence:
R -> W -> NOP -> W -> R -> NOP -> R -> NOP -> NOP -> W -> R -> W.
In this case the Reads stay “in phase” because they occur 2 or 4 cycles apart. Consequently, when a Read occurs in cycle “n”, the
operation in cycle “n-4” is always a Read or NOP, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where an even number of NOPs are inserted into the typical sequence:
R -> W -> NOP -> NOP -> R-> W -> R -> NOP -> NOP -> W -> R -> W -> R -> W -> R -> W.
In this case the Reads stay “in phase” because they occur 2 or 4 cycles apart. Consequently, when a Read occurs in cycle “n”, the
operation in cycle “n-4” is always a Read or NOP, and therefore this bank restriction is automatically avoided.
Now consider the following sequence, where an odd number of NOPs are inserted into the typical sequence:
R -> W -> NOP -> R -> W -> R -> W -> R -> NOP -> W -> R -> W -> NOP -> NOP -> NOP -> R -> W.
In this case the Reads become “out of phase” because they sometimes occur 3 or 5 cycles apart. Consequently, when a Read occurs
in cycle “n”, the operation in cycle “n-4” is sometimes a Write (see the red bolded Reads for examples where this occurs), and there-
fore this bank restriction must be taken into consideration when the Reads are initiated.
Rev: 1.09 5/2016
19/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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