GS8672D36BE-200 Datasheet, PDF (17/29 Pages) GSI Technology – 72Mb SigmaQuad-II Burst of 4 ECCRAM

GS8672D18/36BE-400/333/300/250/200
AC Electrical Characteristics
Parameter
Symbol
-400
Min Max
-333
Min Max
-300
Min Max
-250
Min Max
Hold Times
Address Input Hold Time
t_KHAX
0.4
—
0.4
—
0.4
—
0.5
—
Control Input Hold Time (R, W)
t_KHIX
0.4
—
0.4
—
0.4
—
0.5
—
Control Input Setup Time
(BWX)
t_IVKH
0.28
—
0.28
—
0.3
—
0.35
—
Data Input Hold Time
t_KHDX
0.28
—
0.28
—
0.3
—
0.35
—
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W.
3. Control signals are BW0, BW1, and (BW2, BW3 for x36).
4. If C, C are tied high, K, K become the references for C, C timing parameters
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
-200
Min Max
0.6
— ns 1
0.6
— ns 2
0.4
— ns 3
0.4
— ns
Rev: 1.02a 8/2017
17/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology