GS82582D18GE-333I Datasheet, PDF (17/30 Pages) GSI Technology – 288Mb SigmaQuad-IITM Burst of 4 SRAM

GS82582D18/36GE-400/375/333/300/250
AC Electrical Characteristics
Parameter
-400
-375
Symbol
Min Max Min Max
-333
Min Max
-300
Min Max
-250
Units Notes
Min Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
t_KHKH
t_CHCH
2.5 8.4 2.66 8.4
3.0
8.4 3.3
8.4
4.0 8.4
ns
tKC Variable
t_KCVar
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
ns
6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
t_KHKL
t_CHCL
1.0
— 1.06 —
1.2
— 1.32 —
1.6
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
t_KLKH
t_CLCH
1.0
— 1.06 —
1.2
— 1.32 —
1.6
—
ns
K to K High
C to C High
t_KHKH
t_CHCH
1.05 — 1.13 —
1.35
— 1.49
—
1.8
—
ns
K to K High
C to C High
t_KHKH
t_CHCH
1.05 — 1.13 —
1.35
— 1.49
—
1.8
—
ns
K, K Clock High to C, C Clock High
t_KHCH
0 1.13 0 1.21
0
1.35 0
1.49
0
1.8
ns
DLL Lock Time
t_KLock
1024 — 1024 —
1024
— 1024
—
1024 —
cycle
7
K Static to DLL reset
t_KReset
30
—
30
—
30
—
30
—
30
—
ns
K, K Clock Initialization
Output Times
t_KInit
20 — 20 —
20
— 20 —
20 —
s
9
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
t_KHQV
t_CHQV
— 0.45 — 0.45
—
0.45 —
0.45
—
0.45
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
t_KHQX
t_CHQX
–0.45 — –0.45 —
–0.45
— –0.45
—
–0.45 —
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
t_KHCQV
t_CHCQV
— 0.45 — 0.45
—
0.45 —
0.45
— 0.45
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
t_KHCQX
t_CHCQX
–0.45
—
–0.45
—
–0.45
— –0.45
—
–0.45 —
ns
CQ, CQ High Output Valid
t_CQHQV
—
0.2
—
0.2
—
0.25 —
0.27
—
0.30
ns
8
CQ, CQ High Output Hold
t_CQHQX
–0.2
—
–0.2
—
–0.25
— –0.27
—
–0.30 —
ns
8
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
1.0
—
1.0
—
1.10
— 1.24
—
1.55 —
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
t_KHQZ
t_CHQZ
— 0.45 — 0.45
—
0.45 —
0.45
—
0.45
ns
4
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W
3. Control signals are BW0, BW1 (and BW2, BW3 for x36).
4. If C, C are tied high, K, K become the references for C, C timing parameters
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
8. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
9. After device power-up, 20s of stable input clocks (as specified by t_KInit) must be supplied before reads and writes are issued.
Rev: 1.04 4/2016
17/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology