GS8673ET18 Datasheet, PDF(16/34 Page) GSI Technology – 72Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

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GS8673ET18 Datasheet, PDF (16/34 Pages) GSI Technology – 72Mb SigmaDDR-IIIe™ Burst of 2 ECCRAM™

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GS8673ET18/36BK-675/625/550/500

Output Driver Impedance Control

Programmable output drivers have been implemented on Read Data (DQ), Read Data Valid (QVLD), and Echo Clocks (CQ, CQ).

The output driver impedance can be programmed via the ZQ pin. When an external impedance-matching resistor (RQ) is

connected between ZQ and VSS, output driver impedance is set to RQ/5 nominally.

Output driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,

and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the

system.

Input Termination Impedance Control

On-die input termination can be enabled on Write Data (DQ) Address (SA), Control (LD, R/W, AZT1), and Input Clocks (CK, CK,

KD, KD) via the MZT[1:0] and PZT[1:0] pins. The termination impedance can be programmed via the ZT pin. When an external

impedance-matching resistor (RT) is connected between ZT and VSS, termination impedance is set according to the table below.

Termination impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,

and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the

system.

Note: When termination impedance is enabled on a particular input, that input should always be driven High or Low; it should

never be tri-stated (i.e., in a High-Z state). If the input is tri-stated, the termination will pull the signal to VDDQ / 2 (i.e., to the

switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it

normally would. This could result in the deviceâs operating currents being higher.

The following table specifies the pull-up and pull-down termination impedances for each terminated input:

Pull-up and Pull-Down Termination Impedance

Terminated Inputs

PZT[1:0] MZT[1:0]

CK, CK, KD, KD

SA, LD, R/W, AZT1

Notes:

1. When MZT[1:0] = 00, input termination is disabled on all inputs.

2. When MZT[1:0] = 11, input termination state is not specified; it is reserved for future use.

3. During JTAG EXTEST and SAMPLE-Z instructions, input termination is disabled on all inputs.

Pull-Down

Impedance

disabled

2 * RT

disabled

2 * RT

Pull-Up

Impedance

disabled

2 * RT

disabled

2 * RT

Rev: 1.06 5/2012

16/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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