GS8182D37BGD-375 Datasheet, PDF (16/27 Pages) GSI Technology – 18Mb SigmaQuad-II+ Burst of 4 SRAM

GS8182D19/37BD-435/400/375/333/300
AC Electrical Characteristics (Continued)
Parameter
Symbol
-435
Min Max
-400
Min Max
-375
Min Max
-333
Min Max
-300
Min Max
Hold Times
Address Input Hold Time
Control Input Hold Time
(R, W)
Control Input Hold Time
(BWX) (NWX)
t_KHAX
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
ns 1
t_KHIX
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
ns 2
t_KHIX
0.28
—
0.28
—
0.28
—
0.28
—
0.28
—
ns 3
Data Input Hold Time
t_KHDX
0.28
—
0.28
—
0.28
—
0.28
—
0.28
—
ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,
3. Control singles are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-
tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX
parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-
tures.
6. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
Rev: 1.03a 11/2011
16/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology