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GS81314LQ19GK-933I Datasheet, PDF (15/39 Pages) GSI Technology – Burst of 2 Single-Bank ECCRAM | |||
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GS81314LQ19/37GK-933/800
Changing Loopback Modes
Once enabled, Loopback Mode can be changed as follows
Step 1: Initiate a Register Write operation with SA[10:1] = â000cd1.0010â to select Register #2, keep LBKE = 1 to keep
Loopback Mode enabled, and set LBK[1:0] to âcdâ to select Loopback Mode âcdâ.
Step 2: Wait 16 cycles for new register settings to take effect.
Loopback Mode âcdâ is enabled after step 2 because MRW = 0, LBKE = 1, and LBK[1:0] = âcdâ.
Disabling Loopback Mode
Loopback Mode is disabled as follows:
Step 1: Initiate a Register Write operation with SA[10:1] = â000xx0.0010â to select Register #2 and set LBKE = 0 to disable
Loopback Mode.
Step 2: Wait 16 cycles for new register settings to take effect.
Loopback Mode is disabled after step 2 because LBKE = 0.
XOR LBK Mode
XOR LBK Mode is for address/control input training. It is defined as follows:
⢠Each input pin of the selected input group is sampled on ïCK and ïCK.
⢠For each input sampled, the value sampled on ïCK is XORed with the value sampled on ïCK.
⢠For each input sampled, the XOR result is subsequently driven out on its associated output pin (concurrently with ïCQ) for one
full clock cycle, beginning âLBKLâ cycles after the input is sampled.
Consequently, the output data pattern is always SDR regardless of the input data pattern, and regardless whether the SRAM
samples the inputs correctly or not. The SDR output data pattern enables address/control inputs to be trained before data outputs.
XOR LBK Mode enables the controller to input various SDR and DDR data patterns on a particular input, and then determine
whether the SRAM sampled them correctly or not by observing SDR data patterns on the associated output. Via multiple iterations
of this process, the controller can adjust its output timing (in order to adjust the SRAM input timing) until optimum setup and hold
margin at both SRAM input sample points is achieved, thereby individually âtrainingâ each address/control input pin.
INV LBK Mode
INV LBK Mode is primarily for read data output training. It is defined as follows:
⢠Each input pin of the selected input group is sampled on ïCK and ïCK.
⢠For each input sampled, the value sampled on ïCK is subsequently driven out on its associated output pin (concurrently with
ïCQ) for half a clock cycle, beginning âLBKLâ cycles after the input is sampled.
⢠For each input sampled, the value sampled on ïCK is inverted and then subsequently driven out on its associated output pin (con-
currently with ïCQ) for half a clock cycle, beginning âLBKL + 0.5â cycles after the input is sampled.
Consequently, the output data pattern is DDR if the input data pattern is SDR (and vice versa), provided the SRAM samples the
inputs correctly. Therefore, to ensure deterministic output behavior, address/control inputs should be trained before data outputs.
INV LBK Mode enables the controller to input various SDR (or DDR) data patterns on a particular input, to generate deterministic
DDR (or SDR) data patterns on a particular output. The controller latches the output as it would during a normal Read operation,
and verifies whether it received the expected values or not. Via multiple iterations of this process, the controller can adjust its input
timing until optimum setup and hold margin at both controller input sample points is achieved, thereby individually âtrainingâ each
read data output pin.
Note: INV LBK Mode can be used for address/control input training, if desired. However, such usage can be problematic because
the output data pattern may be erroneous (i.e. it could be SDR or DDR regardless of the input pattern) if the SRAM samples the
input incorrectly. In which case the controller may have difficulty detecting the erroneous behavior, and/or interpreting it.
Rev: 1.02 3/2016
15/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
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