GS81302Q07GE-250I Datasheet, PDF (15/28 Pages) GSI Technology – 144Mb SigmaQuad-II+TM Burst of 2 SRAM

GS81302Q07/10/19/37E-318/300/250/200
AC Electrical Characteristics
Parameter
Symbol
-318
Min Max
-300
Min Max
-250
Min Max
-200
Min Max
Clock
K, K Clock Cycle Time
t_KHKH
3.145 8.4
3.3
8.4
4.0
8.4
5.0
8.4
tK Variable
t_KVar
— 0.2
—
0.2
—
0.2
—
0.2
K, K Clock High Pulse Width
t_KHKL
1.2 —
1.32
—
1.6
—
2.0
—
K, K Clock Low Pulse Width
t_KLKH
1.2 —
1.32
—
1.6
—
2.0
—
K to K High
t_KHKH
1.28 —
1.49
—
1.8
—
2.2
—
K to K High
t_KHKH
1.28 —
1.49
—
1.8
—
2.2
—
DLL Lock Time
t_KCLock
2048 —
2048
—
2048
—
2048
—
K Static to DLL reset
Output Times
t_KCReset
30
—
30
—
30
—
30
—
K, K Clock High to Data Output Valid
t_KHQV
— 0.45
—
0.45
—
0.45
—
0.45
K, K Clock High to Data Output Hold
t_KHQX
–0.45 —
–0.45
—
–0.45
—
–0.45
—
K, K Clock High to Echo Clock Valid
t_KHCQV
— 0.45
—
0.45
—
0.45
—
0.45
K, K Clock High to Echo Clock Hold
t_KHCQX
–0.45 —
–0.45
—
–0.45
—
–0.45
—
CQ, CQ High Output Valid
t_CQHQV
— 0.25
—
0.27
—
0.30
—
0.35
CQ, CQ High Output Hold
t_CQHQX
–0.25
—
–0.27
—
–0.30
—
–0.35
—
CQ, CQ High to QVLD
t_QVLD
–0.25 0.25 –0.27
0.27
–0.30
0.30
–0.35
0.35
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
1.10
—
1.24
—
1.55
—
1.95
—
K Clock High to Data Output High-Z
t_KHQZ
— 0.45
—
0.45
—
0.45
—
0.45
K Clock High to Data Output Low-Z
Setup Times
t_KHQX1
–0.45 —
–0.45
—
–0.45
—
–0.45
—
Address Input Setup Time
t_AVKH
0.28 —
0.30
—
0.35
—
0.4
—
Control Input Setup Time (R, W)
t_IVKH
0.28 —
0.30
—
0.35
—
0.4
—
Control Input Setup Time (BWX) (BWX)
t_IVKH
0.28 —
0.30
—
0.35
—
0.4
—
Data Input Setup Time
Hold Times
t_DVKH
0.28 —
0.30
—
0.35
—
0.4
—
Address Input Hold Time
t_KHAX
0.28 —
0.30
—
0.35
—
0.4
—
Control Input Hold Time (R, W)
t_KHIX
0.28 —
0.30
—
0.35
—
0.4
—
Control Input Hold Time (BWX) (BWX)
t_KHIX
0.28 —
0.30
—
0.35
—
0.4
—
Data Input Hold Time
t_KHDX
0.28 —
0.30
—
0.35
—
0.4
—
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W
3. Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
Units
ns
ns
ns
ns
ns
ns
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
5
1
2
3
1
2
3
Rev: 1.02f 8/2017
15/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology