GS82582Q20GE-450I Datasheet, PDF (14/25 Pages) GSI Technology – 288Mb SigmaQuad-II Burst of 2 SRAM

GS82582Q20/38GE-500/450/400/375
AC Electrical Characteristics
Parameter
Symbol
-500
Min Max
-450
Min Max
-400
Min Max
-375
Min Max
Clock
K, K Clock Cycle Time
t_KHKH
2.0 8.4
2.2
8.4
2.5
8.4
2.66
8.4
tK Variable
t_KVar
— 0.15
—
0.15
—
0.2
—
0.2
K, K Clock High Pulse Width
t_KHKL
0.4 —
0.4
—
0.4
—
0.4
—
K, K Clock Low Pulse Width
t_KLKH
0.4 —
0.4
—
0.4
—
0.4
—
K to K High
t_KHKH
0.85 —
0.94
—
1.06
—
1.13
—
K to K High
t_KHKH
0.85 —
0.94
—
1.06
—
1.13
—
DLL Lock Time
t_KLock
2048 —
2048
—
2048
—
2048
—
K Static to DLL reset
t_KReset
30
—
30
—
30
—
30
—
K, K Clock Initialization
Output Times
t_KInit
20 —
20
—
20
—
20
—
K, K Clock High to Data Output Valid
t_KHQV
— 0.45
—
0.45
—
0.45
—
0.45
K, K Clock High to Data Output Hold
t_KHQX
–0.45 —
–0.45
—
–0.45
—
–0.45
—
K, K Clock High to Echo Clock Valid
t_KHCQV
— 0.33
—
0.37
—
0.45
—
0.45
K, K Clock High to Echo Clock Hold
t_KHCQX
–0.33 —
–0.37
—
–0.45
—
–0.45
—
CQ, CQ High Output Valid
t_CQHQV
— 0.15
—
0.15
—
0.2
—
0.23
CQ, CQ High Output Hold
t_CQHQX
–0.15
—
–0.15
—
–0.2
—
–0.23
—
CQ, CQ High to QVLD
t_QVLD
–0.15 0.15 –0.15
0.15
–0.2
0.2
–0.23
0.23
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
0.75
—
0.85
—
1.0
—
1.0
—
K Clock High to Data Output High-Z
t_KHQZ
— 0.45
—
0.45
—
0.45
—
0.45
K Clock High to Data Output Low-Z
Setup Times
t_KHQX1
–0.45 —
–0.45
—
–0.45
—
–0.45
—
Address Input Setup Time
t_AVKH
0.25 — 0.275
—
0.4
—
0.4
—
Control Input Setup Time (R, W)
t_IVKH
0.25 — 0.275
—
0.4
—
0.4
—
Control Input Setup Time (BWX) (BWX)
t_IVKH
0.20 —
0.22
—
0.28
—
0.28
—
Data Input Setup Time
Hold Times
t_DVKH
0.20 —
0.22
—
0.28
—
0.28
—
Address Input Hold Time
t_KHAX
0.25 — 0.275
—
0.4
—
0.4
—
Control Input Hold Time (R, W)
t_KHIX
0.25 — 0.275
—
0.4
—
0.4
—
Control Input Hold Time (BWX) (BWX)
t_KHIX
0.20 —
0.22
—
0.28
—
0.28
—
Data Input Hold Time
t_KHDX
0.20 —
0.22
—
0.28
—
0.28
—
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W
3. Control signals are BW0, BW1 (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. After device power-up, 20s of stable input clocks (as specified by t_KInit) must be supplied before reads and writes are issued.
Units
ns
ns
ns
ns
ns
ns
cycle
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
5
6
1
2
3
1
2
3
Rev: 1.04 4/2016
14/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology