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GS816272CC-V Datasheet, PDF (14/29 Pages) GSI Technology – 256K x 72 18Mb S/DCD Sync Burst SRAMs | |||
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Preliminary
GS816272CC-xxxV
AC Electrical Characteristics
Parameter
Symbol
-250
Min
Max
-200
Min
Max
-150
Unit
Min
Max
Pipeline
Flow Through
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
Hold time
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
Hold time
tKC
4.0
â
5.0
â
6.7
â
ns
tKQ
â
3.0
â
3.0
â
3.8
ns
tKQX
1.5
â
1.5
â
1.5
â
ns
tLZ1
1.5
â
1.5
â
1.5
â
ns
tS
1.5
â
1.5
â
1.5
â
ns
tH
0.2
â
0.4
â
0.5
â
ns
tKC
5.5
â
6.5
â
7.5
â
ns
tKQ
â
5.5
â
6.5
â
7.5
ns
tKQX
2.0
â
â
6.5
â
7.5
ns
tLZ1
2.0
â
2.0
â
2.0
â
ns
tS
1.5
â
1.5
â
1.5
â
ns
tH
0.5
â
0.5
â
0.5
â
ns
Clock HIGH Time
tKH
1.3
â
1.3
â
1.5
â
ns
Clock LOW Time
tKL
1.7
â
1.7
â
1.7
â
ns
Clock to Output in
High-Z
tHZ1
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
â
3.0
â
3.0
â
3.8
ns
G to output in Low-Z
G to output in High-Z
ZZ setup time
ZZ hold time
tOLZ1
tOHZ1
tZZS2
tZZH2
0
â
0
â
0
â
ns
â
3.0
â
3.0
â
3.8
ns
5
â
5
â
5
â
ns
1
â
1
â
1
â
ns
ZZ recovery
tZZR
20
â
20
â
20
â
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.02a 6/2006
14/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
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