GS8182D19BD-333I Datasheet, PDF (12/27 Pages) GSI Technology – JEDEC-standard pinout and package

GS8182D19/37BD-435/400/375/333/300
Undershoot Measurement and Timing
V_IH
V_SS
50%
V_SS – 1.0 V
20% tKHKH
Capacitance
(T_A = 25^oC, f = 1 MHZ, V_DD = 1.8 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
C_IN
C_OUT
C_CLK
Overshoot Measurement and Timing
V_DD + 1.0 V
50%
20% tKHKH
V_DD
V_IL
Test conditions
V_IN = 0 V
V_OUT = 0 V
V_IN = 0 V
Typ.
Max.
Unit
4
5
pF
6
7
pF
5
6
pF
AC Test Conditions
Parameter
Input high level
Input low level
Max. input slew rate
Input reference level
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
1.25 V
0.25 V
2 V/ns
0.75 V
V_DDQ/2
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
50Ω
V_REF = 0.75 V
VT = V_DDQ/2
Rev: 1.03a 11/2011
12/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2008, GSI Technology