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GS81302D38E-500 Datasheet, PDF (12/31 Pages) GSI Technology – 144Mb SigmaQuad-II+ Burst of 4 SRAM | |||
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GS81302D06/11/20/38E-500/450/400/350
Nybble Write Clock Truth Table
NW
NW
NW
NW
Current Operation
D
D
D
D
Kï
(tn+1)
T
Kï
(tn+1½)
T
Kï
(tn+2)
T
Kï
(tn+2½)
T
Kï
(tn)
Write
Dx stored if NWn = 0 in all four data transfers
Kï
(tn+1)
D0
Kï
(tn+1½)
D2
Kï
(tn+2)
D3
Kï
(tn+2½)
D4
T
F
F
F
Write
Dx stored if NWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
X
D2
X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
X
X
D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
Notes:
1. â1â = input âhighâ; â0â = input âlowâ; âXâ = input âdonât careâ; âTâ = input âtrueâ; âFâ = input âfalseâ.
2. If one or more NWn = 0, then NW = âTâ, else NW = âFâ.
x8 Nybble Write Enable (NWn) Truth Table
NW0
NW1
1
1
0
1
1
0
0
0
D0âD3
Donât Care
Data In
Donât Care
Data In
D4âD7
Donât Care
Donât Care
Data In
Data In
Rev: 1.05c 8/2017
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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