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GS81302D09E-350 Datasheet, PDF (12/34 Pages) GSI Technology – 144Mb SigmaQuadTM-II Burst of 4 SRAM | |||
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GS81302D08/09/18/36E-375/350/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175ï and 350ï. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAMâs output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
D0âD8
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D9âD17
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D18âD26
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D27âD35
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x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
1
1
0
1
1
0
0
0
D0âD8
Donât Care
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Donât Care
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D9âD17
Donât Care
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Data In
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Rev: 1.04c 8/2017
12/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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