GS81302D37AGD-333 Datasheet, PDF (11/25 Pages) GSI Technology – JEDEC-standard pinout and package

Preliminary
GS81302D19/37AGD-450/400/375/333
Capacitance
(T_A = 25^oC, f = 1 MHZ, V_DD = 1.8 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
C_IN
C_OUT
C_CLK
Test conditions
V_IN = 0 V
V_OUT = 0 V
V_IN = 0 V
AC Test Conditions
Parameter
Input high level
Input low level
Max. input slew rate
Input reference level
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
Typ.
Max.
4
5
6
7
5
6
Conditions
1.25
0.25 V
2 V/ns
0.75
V_DDQ/2
AC Test Load Diagram
DQ
RQ = 250 (HSTL I/O)
50
V_REF = 0.75 V
VT == 0.75 V
Input and Output Leakage Characteristics
Parameter
Input Leakage Current
(except mode pins)
Doff
ODT
Symbol
I_IL
I_ILDOFF
I_{IL ODT}
Output Leakage Current
I_OL
Test Conditions
V_IN = 0 to V_DD
V_IN = 0 to V_DD
V_IN = 0 to V_DD
Output Disable,
V_OUT = 0 to V_DDQ
Min.
–2 uA
–2 uA
–2 uA
–2 uA
Unit
pF
pF
pF
Max
2 uA
100 uA
100 uA
2 uA
Rev: 1.00a 5/2017
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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