GS8321Z18E-V Datasheet, PDF (10/32 Pages) GSI Technology – 36Mb Pipelined and Flow Through Synchronous NBT SRAMs

Pipeline Mode Data I/O State Diagram
GS8321Z18/32/36E-xxxV
Intermediate
BW
R
High Z
(Data In)
D
Intermediate
Intermediate
W
Intermediate
RB
Data Out
(Q Valid)
D
Intermediate
WR
High Z
B
D
Intermediate
Key
Input Command Code
ƒ _Transition
Transition
Current State (n) Intermediate State (N+1) Next State (n+2)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n
Clock (CK)
n+1
n+2
n+3
Command
ƒ
ƒ
ƒ
ƒ
Current State
Intermediate
State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.05 6/2006
10/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology