GS8320E18T Datasheet, PDF (10/25 Pages) GSI Technology – 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
W
R
W
R
X
First Write ^R
CW
CR
First Read
X
CR
W
R
X Burst Write
CR
CW
R
Burst Read
X
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.01 10/2004
10/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology