GS82582D36E-375 Datasheet, PDF (10/30 Pages) GSI Technology – 288Mb SigmaQuad-IITM Burst of 4 SRAM

GS82582D18/36GE-400/375/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20 s prior to issuing read and write commands. See the t_KInit
timing parameter in the AC Electrical Characteristics section.
Note:
The t_KInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, t_KInit is greater than t_KLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2 s). Consequently, the 20 s associated with t_KInit is sufficient to cover the t_KLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20 s period.
Also, t_KInit only needs to be met once, immediately after power-up, whereas t_KLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
D0–D8
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D9–D17
Don’t Care
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Don’t Care
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Don’t Care
Don’t Care
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Data In
Don’t Care
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D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
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Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Rev: 1.04 4/2016
10/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology