GS882ZV18BB Datasheet, PDF (1/33 Pages) GSI Technology – 9Mb Pipelined and Flow Through Synchronous NBT SRAM

GS882ZV18/36BB/D-333/300/250/200
119-bump and 165-bump BGA
Commercial Temp
Industrial Temp
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz–200 MHz
1.8 V V_DD
1.8 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
packages
• Pb-Free 119-bump and 165-bump BGA packages available
Functional Description
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS882ZV18/36B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS882ZV18/36B is a 9Mbit Synchronous Static SRAM.
The GS882ZV18/36B is implemented with GSI's high
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
performance CMOS technology and is available in JEDEC-
pipelined read/double late write or flow through read/single
standard 119-bump BGA and 165-bump FPBGA packages.
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Paramter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
-333 -300 -250 -200 Unit
2.5
2.5
2.5
3.0
ns
3.0
3.3
4.0
5.0
ns
245
225
195
165
mA
275
250
220
185
mA
4.5
5.0
5.5
6.5
ns
4.5
5.0
5.5
6.5
ns
195
180
155
140
mA
220
200
175
155
mA
Rev: 1.03 3/2005
1/33
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
© 2004, GSI Technology