GS882Z18BB-V Datasheet, PDF (1/33 Pages) GSI Technology – 9Mb Pipelined and Flow Through Synchronous NBT SRAM

GS882Z18/36B(B/D)-xxxV
119-bump and 165-bump BGA
Commercial Temp
Industrial Temp
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• Pin-compatible with 2M, 4M, and 18M devices
The GGS882Z18/36B(B/D)-xxxV may be configured by the
• Byte write operation (9-bit Bytes)
user to operate in Pipeline or Flow Through mode. Operating
• 3 chip enable signals for easy depth expansion
as a pipelined synchronous device, in addition to the rising-
• ZZ Pin for automatic power-down
edge-triggered registers that capture input signals, the device
• JEDEC-standard 119-bump BGA and 165-bump FPBGA
incorporates a rising edge triggered output register. For read
packages
cycles, pipelined SRAM output data is temporarily stored by
• RoHS-compliant 119-bump and 165-bump BGA packages
the edge-triggered output register during the access cycle and
available
then released to the output drivers at the next rising edge of
clock.
Functional Description
The GS882Z18/36B(B/D)-xxxV is implemented with GSI's
The GS882Z18/36B(B/D)-xxxV is a 9Mbit Synchronous Static _{high performance CMOS technology and is available in}
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
JEDEC-standard 119-bump BGA and 165-bump FPBGA
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
packages.
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Paramter Synopsis
-250
-200 -150 Unit
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
3.0
3.0
3.8
ns
4.0
5.0
6.7
ns
195
165
140
mA
220
185
160
mA
5.5
6.5
7.5
ns
5.5
6.5
7.5
ns
155
140
128
mA
175
155
145
mA
Rev: 1.04 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
© 2004, GSI Technology