GS882V18BB Datasheet, PDF (1/36 Pages) GSI Technology – 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

GS882V18/36BB/D-333/300/250/200
119- and 165-Bump BGA
Commercial Temp
Industrial Temp
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
333 MHz–200 MHz
1.8 V V_DD
1.8 V I/O
Features
Data Output Register. Holding FT high places the RAM in
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
• IEEE 1149.1 JTAG-compatible Boundary Scan
SCD and DCD Pipelined Reads
• On-chip read parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 165-bump BGA packages
• Pb-Free 119-bump and 165-bump packages available
Functional Description
Applications
The GS882V18/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
The GS882V18/36B is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
DCD SRAMs pipeline disable commands to the same degree
as read commands. SCD SRAMs pipeline deselect commands
one stage less than read commands. SCD RAMs begin turning
off their outputs immediately after the deselect command has
been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure this SRAM for either mode of operation using
the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
burst addresses are generated internally and are controlled by
Core and Interface Voltages
ADV. The burst address counter may be configured to count in
The GS882V18/36B operates on a 2.5 V or 3.3 V power
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V_DDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Paramter Synopsis
-333 -300 -250 -200 Unit
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
2.5
2.5
3.0
ns
3.0
3.3
4.0
5.0
ns
245
225
195
165
mA
275
250
220
185
mA
4.5
5.0
5.5
6.5
ns
4.5
5.0
5.5
6.5
ns
195
180
155
140
mA
220
200
175
155
mA
Rev: 1.02 3/2005
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology