GS881E18BT Datasheet, PDF (1/40 Pages) GSI Technology – 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
100-Pin TQFP & 165-bump BGA _{512K x 18, 256K x 32, 256K x 36}
Commercial Temp
Industrial Temp
9Mb Sync Burst SRAMs
250 MHz–150 MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
Linear Burst Order (LBO) input. The Burst function need not
• FT pin for user-configurable flow through or pipeline
operation
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
• Dual Cycle Deselect (DCD) operation
Flow Through/Pipeline Reads
• IEEE 1149.1 JTAG-compatible Boundary Scan
The function of the Data Output register can be controlled by
• 2.5 V or 3.3 V +10%/–10% core power supply
the user via the FT mode pin (Pin 14). Holding the FT mode
• 2.5 V or 3.3 V I/O supply
pin low places the RAM in Flow Through mode, causing
• LBO pin for Linear or Interleaved Burst mode
output data to bypass the Data Output Register. Holding FT
• Internal input resistors on mode pins allow floating mode pins high places the RAM in Pipeline mode, activating the rising-
• Default to Interleaved Pipeline mode
edge-triggered Data Output Register.
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
• Pb-Free 100-lead TQFP and 165-bump BGA packages
available
DCD Pipelined Reads
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a DCD (Dual Cycle Deselect) pipelined synchronous
SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the
same degree as read commands. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
Functional Description
Applications
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a 9,437,184-bit high performance synchronous SRAM with
a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V_DDQ) pins are
be initiated with either ADSP or ADSC inputs. In Burst mode, used to decouple output noise from the internal circuits and are
subsequent burst addresses are generated internally and are
3.3 V and 2.5 V compatible.
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Paramter Synopsis
-333 -300 -250 -200 -150 Unit
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
2.5
2.5
3.0
3.8
ns
3.0
3.3
4.0
5.0
6.7
ns
250
230
200
170
140
mA
290
265
230
195
160
mA
4.5
5.0
5.5
6.5
7.5
ns
4.5
5.0
5.5
6.5
7.5
ns
200
185
160
140
128
mA
230
210
185
160
145
mA
Rev: 1.04 3/2005
1/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology