GS88118BT-V Datasheet, PDF (1/36 Pages) GSI Technology – 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

GS88118/32/36B(T/D)-xxxV
100-pin TQFP & 165-bump BGA _{512K x 18, 256K x 32, 256K x 36}
Commercial Temp
Industrial Temp
9Mb Sync Burst SRAMs
250 MHz–150 MHz
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118/32/36B(T/D)-xxxV is a SCD (Single Cycle
Deselect) pipelined synchronous SRAM. DCD (Dual Cycle
Deselect) versions are also available. SCD SRAMs pipeline
deselect commands one stage less than read commands. SCD
RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers.
Functional Description
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
Applications
(BW) input combined with one or more individual byte write
The GS88118/32/36B(T/D)-xxxV is a 9,437,184-bit high
signals (Bx). In addition, Global Write (GW) is available for
performance synchronous SRAM with a 2-bit burst address
writing all bytes at one time, regardless of the Byte Write
counter. Although of a type originally developed for Level 2
control inputs.
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Core and Interface Voltages
The GS88118/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5 V
power supply. All input are 1.8 V and 2.5 V compatible.
Separate output power (V_DDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V and 2.5 V
compatible.
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Paramter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
-250
3.0
4.0
200
230
5.5
5.5
160
185
-200
3.0
5.0
170
195
6.5
6.5
140
160
-150
Unit
3.8
ns
6.7
ns
140
mA
160
mA
7.5
ns
7.5
ns
128
mA
145
mA
Rev: 1.00 6/2006
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology