GS880Z18AT-133 Datasheet, PDF (1/25 Pages) GSI Technology – 9Mb Pipelined and Flow Through Synchronous NBT SRAM

GS880Z18/36AT-250/225/200/166/150/133
100-Pin TQFP
9Mb Pipelined and Flow Through ^{250 MHz–133 MHz}
Commercial Temp
Industrial Temp
Synchronous NBT SRAM
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
The GS880Z18/36AT is a 9Mbit Synchronous Static SRAM.
read-write-read bus utilization; Fully pin-compatible with
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
both pipelined and flow through NtRAM™, NoBL™ and
pipelined read/double late write or flow through read/single
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
• 2.5 V or 3.3 V I/O supply
when the device is switched from read to write cycles.
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
-250 -225 -200 -166 -150 -133 Unit
Pipeline t_KQ
3-1-1-1 _tCycle
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
3.3 V
Curr (x18) 280 255 230 200 185 165 mA
Curr (x32/x36) 330 300 270 230 215 190 mA
2.5 V
Curr (x18) 275 250 230 195 180 165 mA
Curr (x32/x36) 320 295 265 225 210 185 mA
Flow
Through
2-1-1-1
t_KQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
3.3 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
and simplifies input signal timing.
The GS880Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
2.5 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
clock.
The GS880Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
B
C
D
E
F
Read/Write
R
W
R
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
Q_A
D_B
Q_C
D_D
Q_E
Q_A
D_B
Q_C
D_D
Q_E
Rev: 1.02 9/2002
1/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.