GS880F18BT-V Datasheet, PDF (1/21 Pages) GSI Technology – 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

GS880F18/32/36BT-xxxV
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
5.5 ns–7.5 ns
1.8 V or 2.5 V V_DD
1.8 V or 2.5 V I/O
Features
• Flow Through operation; Pin 14 = No Connect
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with V_SS connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Functional Description
Byte Write and Global Write
Applications
The GS880F18/32/36BT-xxxV is a 9,437,184-bit (8,388,608-
bit for x32 version) high performance synchronous SRAM
with a 2-bit burst address counter. Although of a type
originally developed for Level 2 Cache applications supporting
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
high performance CPUs, the device now finds application in
Sleep Mode
synchronous SRAM applications, ranging from DSP main
Low power (Sleep mode) is attained through the assertion
store to networking chip set support.
(High) of the ZZ signal, or by stopping the clock (CK).
Controls
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst _{Core and Interface Voltages}
control inputs (ADSP, ADSC, ADV), and write control inputs _{The GS880F18/32/36BT-xxxV operates on a 1.8 V or 2.5 V}
(Bx, BW, GW) are synchronous and are controlled by a
power supply. All input are 2.5 V and 1.8 V compatible.
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
Separate output power (V_DDQ) pins are used to decouple
output noise from the internal circuits and are 2.5 V and 1.8 V
compatible.
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Paramter Synopsis
-5.5
-6.5
-150 Unit
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
5.5
6.5
7.5
ns
5.5
6.5
7.5
ns
160
140
128
mA
185
160
145
mA
Rev: 1.00 6/2006
1/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2006, GSI Technology