GS880E18BT Datasheet, PDF (1/28 Pages) GSI Technology – 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

GS880E18/32/36BT-333/300/250/200/150
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
250 MHz–150 MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
Flow Through/Pipeline Reads
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• Internal input resistors on mode pins allow floating mode pins DCD Pipelined Reads
• Default to Interleaved Pipeline mode
The GS880E18/32/36BT is a DCD (Dual Cycle Deselect)
• Byte Write (BW) and/or Global Write (GW) operation
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
• Internal self-timed write cycle
versions are also available. DCD SRAMs pipeline disable
• Automatic power-down for portable applications
commands to the same degree as read commands. DCD RAMs
• JEDEC-standard 100-lead TQFP package
hold the deselect command for one full cycle and then begin
• Pb-Free 100-lead TQFP package available
turning off their outputs just after the second rising edge of
clock.
Functional Description
Byte Write and Global Write
Applications
Byte write operation is performed by using Byte Write enable
The GS880E18/32/36BT is a 9,437,184-bit (8,388,608-bit for (BW) input combined with one or more individual byte write
x32 version) high performance synchronous SRAM with a 2- signals (Bx). In addition, Global Write (GW) is available for
bit burst address counter. Although of a type originally
writing all bytes at one time, regardless of the Byte Write
developed for Level 2 Cache applications supporting high
control inputs.
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Controls
Memory data is retained during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Core and Interface Voltages
The GS880E18/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V_DDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Paramter Synopsis
-333 -300 -250 -200 -150 Unit
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
2.5
2.5
3.0
3.8
ns
3.0
3.3
4.0
5.0
6.7
ns
250
230
200
170
140
mA
290
265
230
195
160
mA
4.5
5.0
5.5
6.5
7.5
ns
4.5
5.0
5.5
6.5
7.5
ns
200
185
160
140
128
mA
230
210
185
160
145
mA
Rev: 1.02 10/2004
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology