GS8672Q18BGE-200I Datasheet, PDF (1/28 Pages) GSI Technology – 72Mb SigmaQuad-II™ Burst of 2 ECCRAM™

GS8672Q18/36BE-400/333/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuad-II™
Burst of 2 ECCRAM™
400 MHz–200 MHz
1.8 V V_DD
1.8 V and 1.5 V I/O
Features
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb, and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ ECCRAM Overview
The GS8672Q18/36BE SigmaQuad-II ECCRAMs are built in
compliance with the SigmaQuad-II SRAM pinout standard for
Separate I/O synchronous SRAMs. They are 75,497,472-bit
(72Mb) ECCRAMs. The GS8672Q18/36BE SigmaQuad-II
ECCRAMs are just one element in a family of Low power,
Low voltage HSTL I/O ECCRAMs designed to operate at the
speeds needed to implement economical High performance
networking systems.
Clocking and Addressing Schemes
The GS8672Q18/36BE SigmaQuad-II ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
High, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaQuad-II B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II B2 ECCRAM is always one address
pin less than the advertised index depth (e.g., the 4M x 18 has
an 2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.02a 8/2017
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology