GS8644Z36GE-200 Datasheet, PDF (1/32 Pages) GSI Technology – 72Mb Pipelined and Flow Through Synchronous NBT SRAM

GS8644Z18E/GS8644Z36E
165-Pin BGA
Commercial Temp
Industrial Temp
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 9Mb, 18Mb, and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 165-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
The GS8644Z18/36 is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8644Z18/36 may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8644Z18/36 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 165-bump BGA package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
t_KQ(x18/x36)
t_KQ(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t_KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
385 360 335 305 295 265 mA
450 415 385 345 325 295 mA
540 505 460 405 385 345 mA
6.5 6.5 6.5 7.0 7.5 8.5 ns
6.5 6.5 6.5 7.0 7.5 8.5 ns
265 265 265 255 240 225 mA
290 290 290 280 265 245 mA
345 345 345 335 315 300 mA
Rev: 1.05b 5/2010
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology