GS8642ZV18B Datasheet, PDF (1/32 Pages) GSI Technology – 72Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C)
119- & 209-Bump BGA
Commercial Temp
Industrial Temp
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–167 MHz
1.8 V V_DD
1.8 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119- or 209-bump BGA package
• Pb-Free 119- and 209-bump BGA packages available
Functional Description
The GS8642ZV18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8642ZV18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8642ZV18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-300 -250 -200 -167 Unit
t_KQ(x18/x36)
t_KQ(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t_KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
2.3
2.5
3.0
3.5
ns
3.0
3.0
3.0
3.5
ns
3.3
4.0
5.0
6.0
ns
400
340
290
260
mA
480
410
350
305
mA
590
520
435
380
mA
5.5
6.5
7.5
8.0
ns
5.5
6.5
7.5
8.0
ns
285
245
220
210
mA
330
280
250
240
mA
425
370
315
300
mA
Rev: 1.02 5/2005
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology