GS8342TT37BGD-450I Datasheet, PDF (1/31 Pages) GSI Technology – 36Mb SigmaDDR-II+TM Burst of 2 SRAM

GS8342TT07/10/19/37BD-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaDDR-II+^TM
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V V_DD
1.8 V or 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
SigmaDDR™ Family Overview
The GS8342TT07/10/19/37BD are built in compliance with
the SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736 (36Mb) SRAMs.
The GS8342TT07/10/19/37BD SigmaDDR-II+ SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342TT07/10/19/37BD SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Common I/O SigmaDDR-II+ RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read
or write transfer, and automatically incremented by 1 for the
next transfer. Because the LSB is tied off internally, the
address field of a SigmaDDR-II+ B2 RAM is always one
address pin less than the advertised index depth force return
(e.g., the 2M x 18 has a 1M addressable index).
Parameter Synopsis
tKHKH
tKHQV
-450
2.22 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.01 6/2012
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology