GS816118C Datasheet, PDF (1/29 Pages) GSI Technology – 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs

Preliminary
GS816118/36CD-333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
1M x 18 and 512K x 36
18Mb Sync Burst SRAMs
333 MHz–250 MHz
2.5 V or 3.3 V V_DD
2.5 V or 3.3 V I/O
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
Functional Description
Applications
The GS816118/36CD is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
SCD Pipelined Reads
The GS816118/36CD is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816118/36CD operates on a 1.8 V power supply. All input
are 1.8 V compatible. Separate output power (V_DDQ) pins are used
to decouple output noise from the internal circuits and are 1.8 V
compatible.
Parameter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
t_KQ
tCycle
Curr (x18)
Curr (x32/x36)
-333 -300 -250 Unit
2.5
2.5
2.5
ns
3.0
3.3
4.0
ns
375
335
280
mA
435
390
330
mA
4.5
5.0
5.5
ns
4.5
5.0
5.5
ns
280
230
210
mA
335
270
240
mA
Rev: 1.00 9/2004
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology